1. Field of the Invention
This invention relates to computer systems and more particularly to transitioning computer systems between various power states.
2. Description of the Related Art
Computer systems have various power savings states in order to provide an appropriate balance between power savings and performance. Many computer systems are compliant with the Advanced Configuration and Power Interface (ACPI). The ACPI specification describes processor core power states to be one of C1-Cn. The greater the index n, the deeper the power state and the smaller the consumed power. Conversely, the deeper the power state, the more time (latency) it takes to return to an execution state. Power savings is achieved by reducing the frequency of the clock and/or reducing the voltage. Voltage may be reduced to a retention level where state is preserved in the core or voltage may be reduced beyond the retention level. Obviously, as state is lost, the latency to resume operation is increased. Further, cache may also have its voltage reduced up to and beyond retention levels. The deeper the power state is, the longer the exit latency in order to resume code execution.
In current computer systems, the North-Bridge (also referred to as Uncore in some embodiments) is a central decision node for transitioning the processor and dynamic random access memory (DRAM) into and out of low power states. Uncore refers to those parts of a processor integrated circuit that are not the processor cores and includes such functionality as the memory controller and power management. Normally the transitioning decision is made in the North-Bridge, following the operating system (OS) request for a specific processor C-state. The depth of the power state is decided, based on internal monitors and activity trackers in the North-Bridge. The exit latency from the power state is one of the factors that can have a detrimental effect on incoming transaction streams or interrupts. The power state entered into is a prediction about future activity, and the odds of misprediction are not negligible. The cost of any misprediction is dependent on the application type being executed, and with some workloads, it may lead to such undesirable effects as dropped frames, dropped packets, and/or underscored performance.
The typical way to avoid misprediction effects is to tune monitors and predictors to more conservative values. This in turn reduces opportunities to enter deeper power states and thus leads to higher dynamic and static power consumption. Another way to avoid the effects of misprediction would be to reduce the exit latency from deep C-states. Thus, even misprediction made by the North-Bridge would be promptly corrected by fast transition of the processor into the execution state with no perceivable performance penalty. However, this approach is more costly since it requires more complicated on-die capabilities/arrays or input/output (I/O) interfaces, therefore impacting performance/cost/watt.